ꠜꠦꠞꠤꠟꠉ
ꠍꠥꠞꠔ ꠢꠣꠟ
ꠜꠦꠞꠤꠟꠉ
ꠎꠦ ꠎꠤꠘꠤꠡꠞ | hardware description language ꠨ modeling language |
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ꠜꠤꠔ꠆ꠔꠤ ꠉꠣꠞꠣ ꠅꠁꠍꠦ | ![]() ![]() ![]() ![]() |
ꠍꠚꠐꠅꠄꠀꠞ ꠜꠣꠞꠡꠘꠞ ꠀꠁꠒꠤ | IEEE ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
ꠎꠦꠐꠣꠄ ꠀꠍꠞ ꠇꠞꠦ | ꠌꠤ ꠨ Pascal ꠨ ꠀꠒꠣ |
programming paradigm | structured programming |
typing discipline | weak typing ꠨ static typing |
file extension | v |
Stack Exchange tag | https://stackoverflow.com/tags/verilog |
ꠅꠐꠣꠕꠘꠦ ꠀꠟꠣꠉ | vlog |
ꠎꠤꠄꠘꠒꠤ ꠀꠁꠒꠤ | 4268385-3 |
ꠁꠎꠞꠣꠁꠟꠤ ꠎꠣꠔꠤꠅ ꠟꠣꠁꠛ꠆ꠛꠦꠞꠤ ꠀꠁꠒꠤ | 987007536924105171 |
Library of Congress authority ID | sh90004761 |
NL CR AUT ID | ph756338 |
FOLDOC ID | Verilog |
ꠚꠤꠞꠤꠛꠦꠁꠍ ꠀꠁꠒꠤ | /m/0h3vb |
ꠜꠦꠞꠤꠟꠉ ꠅꠁꠟꠅ ꠄꠉꠥ ꠇꠝ꠆ꠙꠥꠐꠣꠞꠞ ꠜꠣꠡꠣ ⁕
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