Single-chip Cloud Computer
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| General information | |
|---|---|
| Launched | December 2009 |
| Designed by | Intel Tera-Scale Computing Research Program |
| Performance | |
| Max. CPU clock rate | 1 GHz |
| Physical specifications | |
| Transistors |
|
| Cores |
|
| Memory (RAM) |
|
| Socket |
|
| Cache | |
| L1 cache | 16 KB per core, 4-way set associative |
| L2 cache | 256 KB per core, 4-way set associative |
| Architecture and classification | |
| Technology node | 45 nm transistors |
| Instructions | x86, MIC |
| History | |
| Predecessor | Teraflops Research Chip |
| Successor | Xeon Phi |
The Single-Chip Cloud Computer (SCC) is a computer processor created by Intel Corporation in 2009 with 48 distinct physical cores[1] that communicate through an architecture similar to that of a cloud computer data center. Cores are components of the processor responsible for executing instructions that enable the computer to function. The SCC resulted from an Intel project focusing on researching multi-core processors and parallel processing. Intel also aimed to explore the integration of designs and architecture from large cloud computer data centers (cloud computing) into a single processing chip. The name "Single-chip Cloud Computer" reflects this concept.[2]
Uses
[edit]As of 2010 the SCC was utilized for research purposes. It can run the Linux operating system on the chip, but cannot run Windows.[3] Some applications of the SCC include web servers, data informatics, bioinformatics, and financial analytics.[4]
Technical details
[edit]The cores are spread across the chip but capable of direct communication. The chip comprises 48 P54C Pentium cores connected by a 4×6 2D-mesh of 24 tiles arranged in four rows and six columns. Each tile contains two cores and a 16 KB (8 per core) message passing buffer (MPB) shared by the two cores, essentially functioning as a router.[5] This router enables each core to communicate directly with others, eliminating the need to send information back to the main memory for routing to other cores.[3] The SCC contains 1.3 billion 45 nm transistors capable of amplifying signals or acting as a switch, using 25 to 125 watts of power depending on processing demand. Each chip includes four DDR3 memory controllers connected to the 2D mesh, capable of addressing 64 GB of random-access memory. The DDR3 memory facilitates communication among tiles, contributing to the chip's functionality. These controllers, along with the transistors, manage the activation and deactivation of specific tiles to conserve power when not in use. Proper coding integration results in a functional processor with high speed, power, and energy efficiency, resembling a network of cloud computers.[6]
Modes of operation
[edit]The SCC comes with RCCE, a simple message-passing interface provided by Intel supporting basic message-buffering operations.[5] The SCC operates in two modes: processor mode and mesh mode.
Processor mode
[edit]In processor mode, cores are active, executing code from the system memory, and performing programmed I/O (inputs and outputs) through the system connected to the system board FPGA. Software running on the SCC's embedded management console handles tasks such as loading memory and configuring the processor for bootstrapping (sustaining after the initial load).[7]
Mesh mode
[edit]In mesh mode, cores are turned off, leaving only the routers, transistors, and RAM controllers active. These components send and receive large packets of data without a memory map.[7]
Further plans
[edit]Intel intended to share this technology with other companies, including HP, Yahoo, and Microsoft, to foster collaborative research on the SCC to advance the technology. The goal was to make the SCC scalable to 100+ cores, potentially achieved by enabling communication between individual chips. Intel aimed to enhance parallel programming productivity and power management, leveraging the chip's architecture and numerous cores. Further experimentation were planned on this architecture and similar chip architectures to develop many-core scalable processors maximizing processing power while maintaining energy efficiency.[4]
According to a user seeking software for the SCC in 2025, software was publicly available about ten years before, with programs to communicate directly to the SCC, but the Web site has long been dead.[8]
See also
[edit]References
[edit]- ^ "SCCC PDF from intel.cn" (PDF). Intel | China. Retrieved December 27, 2023.
- ^ Ng, Jason (3 December 2009). "Intel Demonstrates 48-Core "Single-Chip Cloud Computer"". Daily Tech. Archived from the original on 17 December 2009.
- ^ a b Corley, Anne-Marie (9 February 2010). "Intel Lifts the Hood on its "Single-Chip Cloud Computer"". IEEE Spectrum. IEEE. Retrieved 30 October 2014.
- ^ a b Intel Labs Announces Single-chip Cloud Computing Experimental Chip. YouTube (video). Intel. 2 December 2009. Archived from the original on November 12, 2010. Video is unavailable.
- ^ a b Pichel, Juan; Rivera, Francisco (2013). "Sparse matrix–vector multiplication on the Single-Chip Cloud Computer many-core processor". Journal of Parallel and Distributed Computing. 73 (12): 1539–1550. doi:10.1016/j.jpdc.2013.07.017.
- ^ Matson, Tim (2 February 2012). "Using Intel's Single-Chip Cloud Computer (SCC)" (PDF). Intel.com. Intel Corporation. Archived from the original (PDF) on November 29, 2014.
- ^ a b Nerurkar, Nishad; Mhatre, Aniket (9 November 2011). "Overview of the Intel Single Chip Cloud-Computer" (PDF). Archived from the original (PDF) on November 25, 2014.
- ^ "Intel SCC (Single-chip Cloud Computer) Software". [H]ard. 2 July 2025.