Talk:Bit manipulation instructions

ARM11 needs work

ARM11 needs a bit more digging

ARM11 is a microarchitecture. The ARM architecture versions start with ARMv1 and proceed from there, and there's plenty more to do there (checking and possibly adding more details on earlier version, adding ARMv6-M, adding the 32-bit side of ARMv8 including v8-A, v8-R, and v8-M, and adding whatever 32-bit support ARMv9 has, if any - and maybe flagging the ones that are now marked by ARM as obsolete). Then a summary of the versions of the 64-bit sides of ARMv8 and ARMv9 should be done, pointing to AArch64 as the main article. Guy Harris (talk) 12:18, 9 August 2025 (UTC)

i know a bit of the embarrassing unwritten history of ARM, how they were running out of money, and Geoff Bigg from Samsung Research got them a deal for using their early CPU in GPS receivers, they got a royalty-free in-perpetuitary Architectural License for basically saving the company. and how Norman Wilson of LSI Logic fixed all the issues of their HDL bring unsynthesisable :) ARM never designed their own HDL, they got people offering it to them! even Cortex A8 was bought from an Austin VC-funded company after ARM refused to license thumb2 to them! Lkcl (talk) 12:30, 9 August 2025 (UTC)

And then later they gave another architectural license, although I don't know whether it's royalty-free, to one of the non-Acorn companies behind Advanced RISC Machines. It may be that Apple also was significantly involved in the design of the A64 instruction set (they were the first to come out with a 64-bit ARM chip). Guy Harris (talk) 21:17, 9 August 2025 (UTC)

got time

hello reviewers I didn't have time back in 2021 to sort this out, now I do. the false impression by the redirect was being given that ONLY Intel and AMD have bitmanip instructions. this pissed me off as it is so demonstrably false, I have gone overboard to demonstrate the existence of bitmanip instructions in a boatload of architectures.

IBM z/Architecture confusing as hell!

it's clear IBM wanted to drop Cray-vectors in favour of PackedSIMD 128-bit, but what a mess! they had to retain backwards-compatibility and chose to do so only with the Scalar instructions. I suspect the ESA/390 "mode" is a micro-coded emulation of Cray-style vectors Lkcl (talk) 15:43, 7 August 2025 (UTC)

I haven't found the documentation for the ESA/390 vector facility, but the 370, 370-XA, and ESA/370 vector facility option in the 3090 appears to be 1) Cray-like and 2) an additional box lifted into the machine room and plugged into a 3090 processor. Maybe the main CPU decodes the vector instructions and traps if the box isn't present and sends stuff to the box if it is present; how much is done in the main CPU and how much is done in the vector facility of the box, I don't know.

Papers that might be of interest for the 3090 - two IBM Systems Journal articles on the 3090, The IBM System/370 vector architecture on the vector instructions in general, and Vector system performance of the IBM 3090, both paywalled. Also, IBM 3090 Vector Facility Technical Reference, which talks about physical installation on page 35. Guy Harris (talk) 09:23, 8 August 2025 (UTC)

http://www.bitsavers.org/pdf/ibm/390/ reference guide says ES9000 had integrated vector facility, p23, but you had to choose (per CPU?) between it and the crypto module. Lkcl (talk) 13:59, 9 August 2025 (UTC)

IBM_System/390 - ok it's just the year. 360 was 60s, 370 was 70s... and the 370 upwards are all IBM370 compatible. gaah how cute and sane :) so ES9000 is just "370 compatible" Lkcl (talk) 14:07, 9 August 2025 (UTC)

http://www.bitsavers.org/pdf/ibm/370/vectorFacility/ and in the IBM 370 page I know there is a link to the Isa ref manual Lkcl (talk) 14:10, 9 August 2025 (UTC)

reference guide says ES9000 had integrated vector facility, p23, but you had to choose (per CPU?) between it and the crypto module. Yeah, I think both were add-on boxes (the vector facility definitely was), and I guess you could plug in one or the other but not both.

IBM_System/390 - ok it's just the year. 360 was 60s, 370 was 70s... and the 370 upwards are all IBM370 compatible. gaah how cute and sane :) Yeah, this is what happens when you let marketing people give names to products. You get, for example an OS that was originally named so as not to "frighten the horses" by making the name sound a bit like the "Mac OS 9" that it replaced, despite 99 44/100% of the code being either shiny and new or carbonized to work on both, and numbered accordingly, and then "Mac" dropped from "OS X" for a few releaes, and then renamed "macOS" to match all the other OSes as nobody cared about the classic Mac OS any more, and then the numbering went from "10.14" to "11" because you might as well use the same numbering style so the major version number changes every year and you can number small bug-fix releases as dot-dot release, and then saying "**** it let's just number all of our OSes after the year after the year when they're announced".

So the "360" in S/360 was because it covered the "full circle", i.e. 360 degrees, of computing rather than having separate lines of scientific/engineering and business computers (even though there were COBOL compilers for the scientific/engineering machines and FORTRAN compilers for business machines - maybe that's one reason why they decided to go with one line). (A lot of IBM documentation for S/360 had a compass rose on the cover - that's mentioned in Compass rose § Use as symbol.)

I guess somebody in IBM marketing decided to call the followup product line S/360 based an "S/360 for the 1960s" (which it wasn't, but...) -> "S/370 for the 1970s". I've no idea why the 303X, 43XX, 308X, and 3090 dropped that convention, and even for the "System/390 for the 1990s" the individual models weren't "System/390 Model XXX".

I've sometimes snarkily referred to z/Architecture as "System/3100", although I guess it's now "System/3120". :-)

Oh, and that reminds me of more IBM marketing fun. At some point they decided to come out with a letter for each of their lines of computers - "x" for the x86-based servers, "p" for the AIX-running PowerPC/POWER servers, "i" for the AS/400 machines, and 'z' for the now-64-bit mainframes. It was first "IBM eServer [xpiz]System", and then I think went to "System [xpiz]". Somewhere in that time period they sold off the x86 line of machines to Lenovo, so no more "x" stuff, and then they merged the "p" and "i" machines, both using PowerPC/Power ISA POWER microprocessors, into IBM Power Systems, so the only letter left was "z", and they capitalized it and called the mainframes IBM Z.

I think IBM gave some rationale behind at least the non-"x" letters, with "p" maybe being "power" as in "POWER/PowerPC", "i" for "integrated" as in "we have a DBMS integrated into the OS", and "z" for "zero downtime". Guy Harris (talk) 21:08, 9 August 2025 (UTC)

Do boring old bitwise AND, OR, NOT, XOR, etc. count?

They do bit manipulation, but are primitives that can be used, along with other operations, to perform more complicated bit manipulations such as population count and find first set if they're not directly implemented by an instruction. Guy Harris (talk) 00:15, 8 August 2025 (UTC)

Or, to put it another way, do bitwise operations count? Guy Harris (talk) 00:17, 8 August 2025 (UTC)

yeah they are logical bitwise operations, they kinda don't count because they are so ubiquitous like add, but now you mention it I think I worked out what my subconscious was doing, it was noting the unusual ones like AND-complement (A & NOT-B) and OR-complement. those are definitely worth highlighting. brtw thx for correcting IBM3090 Lkcl (talk) 07:58, 8 August 2025 (UTC)

they kinda don't count because they are so ubiquitous It might be worth briefly noting the ones that everybody has - no need to mention them for every ISA listed.

brtw thx for correcting IBM3090 More research in progress. It look as if the eleventh edition of the z/Architecture Principles of Operation is the one that first introduces the z/Architecture vector stuff, about which it says

The vector facility for z/Architecture may be available on models implementing z/Architecture. When the facility is installed and enabled, vector instructions are available, having access to 32 128-bit registers.

and it also says:

Note: ESA/390 provided an optional vector facility, however this facility was never available on any pro- cessor capable of the z/Architecture architectural mode. The vector facility for z/Architecture differs from the ESA/390 vector facility in instruction and register definitions.

Unfortunately, I've yet to find documentation for the ESA/390 vector facility, to see whether it's a (possibly-improper) superset of the 370 vector facility available for the 3090, or if IBM's had three different S/3x0 things with "vector" in their names - or what, if any, ESA/390 machines supported it. Guy Harris (talk) 09:03, 8 August 2025 (UTC)

The same vector architecture applied to all processors prior to z. Neither vector facility has anything to do with the IBM 2938 or 3838.

AND and OR go all the way back to the first generation (vacuum tube) machines. Some later machines, e.g., IBM 7030 Stretch, had "connect" instructions with 4-bit masks to provide all 16 bit-wise operations, some, e.g., PDP-10, had 16 distinct instructions. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 15:03, 8 August 2025 (UTC)

The same vector architecture applied to all processors prior to z. I.e., the ESA/390 vector facility was the same as the 370 vector facility for the 3090? Was anything added to it after the 3090? Any idea what later processors supported it? Guy Harris (talk) 18:37, 8 August 2025 (UTC)

ooooOOoo :) https://hercules-390.github.io/html/#:~:text=The%20Bitsavers%20site%20and%20its%20mirrors%20contain,OCR'd%2C%20IBM%20hardware%20and%20software%20reference%20manuals. Lkcl (talk) 19:16, 8 August 2025 (UTC)

Unfortunately, Bitsavers doesn't have IBM Enterprise Systems Architecture/390 Vector Operations. IBM. SA22-7207., so I can't use it to find out what the ESA/390 vector facility had. Maybe some 390 machine manuals will indicate something about the availability of the vector facility. Guy Harris (talk) 20:19, 8 August 2025 (UTC)

https://bitsavers.org/pdf/ibm/390/GU20-0088_ES9000_Reference_Guide.pdf says that the ES/9000 supported it, although you couldn't get it and the Integrated Cryptographic Facility. They mention the "section size", i.e. the number of elements in a vector register in the 370 vector facility, so it may be similar, and the ES/9000's sector size is 256 rather than the 128 of the 3090. The ISA supports section-size-independent loop code. Guy Harris (talk) 20:32, 8 August 2025 (UTC)

that's called a boolean function aka FPGA LUT2 (or it would be if the 4-bit lookup was an operand rather than an immediate). and I just added the ternary version yesterday, aka avx512/Larrabee vpternlog aka Power ISA xxeval aka LUT3. so that's frickin cool that the 7030 and LDP10 had LUT2. Lkcl (talk) 19:11, 8 August 2025 (UTC)

References

z/Architecture Scalar

The claim These instructions are part of the 11th edition z/Architecture, and are also present in IBM 370 and ESA/390: in § z/Architecture Scalar is wrong. Some of the instructions go all the way back to S/360 and some are new with z/Architecture. Specifically,

S/360

And

Compare logical

Exclusive or

Or

Packed

Rotate

Shift

Test under Mask

S/370

Compare Logical Characters Long (CLCL)

Shift and Round decimal (SRP)

ESA

Load Reversed

Store Reversed

Test decimal (TP)

Test under Mask High

Test under Low

z

And with Complement

Bit Deposit

Bit Extract

Compare Logical and Branch

Compare Logical High (CLHHR, CLHLR, CLHF, CLIH)

Count Leading Zeros

Count Trailing Zeros

Exclusive Or (multiple new versions)

Find Leftmost One

Insert Immediate (multiple new versions)

Load And And

Load And Exclusive or

Load And Or

Load Byte

Load Halfword (multiple new versions)

Load Logical (multiple new versions)

Load on condition (multiple new versions)

Population Count

Store on condition (multiple new versions)

Test under Mask (multiple new versions)

Also, the edition in § References is 15.

I only mentioned SRP and TP because the artical mentioned decimal. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 17:15, 8 August 2025 (UTC)

thank you! yes the confusion is, I was viewing the 11th edition but managed to insert the 15th! ngggh :) so the page numbers are correct but... you get the idea. thank you for helping, this is a complex historical *and* current topic. Lkcl (talk) 19:06, 8 August 2025 (UTC)

Notes

References

TODO add IBM 7030 and PDP10 LUT2

see discussion above (thank you!) but where should it go? bitwise operations? don't kniw Lkcl (talk) 19:13, 8 August 2025 (UTC)

Byte (bit string) operations

Some architectures support variable byte sizes. These include:

IBM 7030

The Variable Field length (VFL) instructions specify a byte length from 1 to 8.

PDP-6, PDP-10

The Byte Manipulation instructions can specify a byte size of 0-36, but it may not straddle word boundaries.

The String Manipulations have a similar restriction.

and p2-99 has BCD.

CDC 3600, 3800

The Variable Data Field instructions specify a byte size of 1-48.

z/Architecture up to version 11

has Search string 7-317 and Search Unicode 7-318, Load count to block boundary 7-230 and Vector of the same 21-8. Vector Load-with-length 21-10 has no conditions/testing like the 3600 had. Vector store with length 21-17

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-- Shmuel (Seymour J.) Metz Username:Chatul (talk) 20:26, 8 August 2025 (UTC)

nice! hmm hmm how to cope, here. originally I subdivided by architecture as top-level but it's getting to... hmmm... by category of instruction subset? Lkcl (talk) 10:43, 9 August 2025 (UTC)

and are these *bit* manipulation or strictly *string* manipulation? it seems a separate page is justifiable here. I am currently on GNFI so kinda have a backlog? :) Lkcl (talk) 10:45, 9 August 2025 (UTC)

oh wait... ok yes *bit* field length, whoa. Lkcl (talk) 11:54, 9 August 2025 (UTC)

ahh okay the 3600 one is a *number of bytes* limited LOAD/STORE/SCAN. I've seen these in z/Architecture (rev11, not rev15 from z13). they're not exactly *bit*-manipulstion but worth a page on their own Lkcl (talk) 12:09, 9 August 2025 (UTC)

Perhaps there's bit manipulation, fixed-point decimal arithmetic or assists for same, and string manipulation (fixed-length or variable-length units). Guy Harris (talk) 12:20, 9 August 2025 (UTC)

yyeah the CDC 3600 conditional-analysis is pretty sparse, and from an HDL perspective I know you'd need to be a total loonie to have an ALU in between the load / store and the registers :) Tom Forsyth explains it well, the mistake made in Larrabee was corrected in KNL see talk on swizzle, appx 30min in https://vimeo.com/450406346 so not holding my breath :) what does tend to happen though is atomic mem-operations, they get used for spin-locks and mutexes. atomic-increment-and-read-at-addr-r3 that sort of thing. slightly different usecase Lkcl (talk) 14:17, 9 August 2025 (UTC)

the only exception I can think of is by-design memory-2-memory or semi-mem2mem like the 8086 (and Atmel PICs etc which have an accumulator and the line between mem up to 2^12 and regs is blurred) Lkcl (talk) 14:50, 9 August 2025 (UTC)

thank you, you prompted me to look at PDP10, I found BCD and LUT2-style logic, which means it has weird And-complement etc. Lkcl (talk) 16:05, 9 August 2025 (UTC)

ha! apparently yes! must read the manual again see if I can understand it https://en.m.wikipedia.org/wiki/Addressing_mode#Indirect_to_bit_field_within_word Lkcl (talk) 20:07, 11 August 2025 (UTC)

"LUT2" presumably meaning "all 16 possible 2-input bitwise Boolean operations". That appears to date back to the PDP-6, which has 16 Boolean instructions (pages 91 and 92 of the PDP-6 Handbook), so that might cover all 16.

As far as I know, the PDP-10 didn't have BCD support in the instruction set until the (microcoded) KL10 and KS10 models with their BCD <-> binary instructions. Are you thinking of those or of something else? Guy Harris (talk) 21:55, 11 August 2025 (UTC)

yes, them's the ones :) the 16 entries is the 4-bit LUT2... LUT4? argh. I can't remember if they are termed by the power 2^N or by the entry size N. the strokes are a damn nuisance. wiped out so much knowledge. PackedBCD fantastic great to have that detail. Lkcl (talk) 06:13, 12 August 2025 (UTC)

i remember (ish) now, it refers to the number of inputs. LUT2 is 2-input with a lookup table of bit-width 2^N, for which there are 2^(2^N) combinations. therefore: LUT2 has a 4-bit table which requires 16 instructions. LUT3 has an 8-bit lookup which needs 256 instructions. Lkcl (talk) 07:14, 12 August 2025 (UTC)

done pdp10 after working out it was bit/offset-length not quantity-of-bytes. Lkcl (talk) 06:30, 12 August 2025 (UTC)

References

z/Arch and 370 now a bit messed up

ok so the 370 the vector facility was optional, and I had put all the refs for scalar and vector based on its manual. the zArch rev1 doc *doesn't* - correctly - have that *optional* set in it. so the Scalar 370 and vector 370 ops which I had separated into two sections have been merged into one. good extra info of the rev1 zArch but the confusion is understandable but persisting Lkcl (talk) 18:58, 9 August 2025 (UTC)

the zArch rev1 doc *doesn't* - correctly - have that *optional* set in it. Yes, it's correct because 370->390 vector facility wasn't optional in z/Architecture, it was non-existent in z/Architecture. Given that it was optional for certain 370/"370-compatible" and 390 machines, they were, I guess, free to drop in in z/Architecture.

My guess, for what it's worth, is that the 3090 and ES/9000 had the vector option in order to compete with Cray in the supercomputer market, and that when "supercomputer", at least as I understand it, switched from vector to MPP (perhaps with the P's in question supporting vector instructions) IBM decided to compete there with MP{PowerPC/Power ISA}P such as Blue Gene/Summit/Sierra. The SIMD stuff IBM put into z/Architecture was probably to compete with other people's SIMD (and complement their own in PowerPC/Power ISA). Guy Harris (talk) 20:31, 9 August 2025 (UTC)

my money's on that the architects for 370 retired and the new team couldn't be bothered to work out how to retain Cray-style SETVL :) SIMD-within-a-register is so much easier for hardware engineers, but absolute hell for ptogrammers. my favourite illustration is a patch to libc6 with a whopping TWO HUNDRED+ PackedSIMD instructions. ironically they added specialist instructions to Power10 (v3.1) similar to SVE2 fault-first but stupidly only for strings... sigh :) Lkcl (talk) 06:35, 12 August 2025 (UTC)

Organization

I've split the main section in two, with one section listing the various types of bit manipulation and the other describing specific architecture. If decimal belongs in the article, what about Gray to binary and binary to Gray instructions?

The material on z/Architecture is confusing; most of what is listed under scalar is vector. Also, should there be any mention of the Neural-Network-Processing-Assist Facility? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 18:17, 12 August 2025 (UTC)

lot going on here, one at a time :) I notice the new types is duplicate of bit manipulation and recommend it be moved/merged there, not least because you discovered some missing areas. yes definitely gray code, converting to gray code is simple: x XOR (x>>1) but the opposite is hell: requires recursive application of that expression. very costly. gray code comes up more than you'd think. don't know about NA yet need to check. tomorrow. late. thx Chatul. Lkcl (talk) 18:59, 12 August 2025 (UTC)

To/from Gray code, definitely; that comes across as manipulating bits.

Decimal, not quite as sure, but doing decimal on mostly-binary machines may be done either with ALU circuits that do odd things (adds that wrap around at 10) or various somewhat bitsy tricks (e.g., the "add a bunch of decimal sixes" trick to force carries - see the Power ISA 3.1 "Add and Generate Sixes" instruction - older versions of PowerPC on processors used in AS/400 machines had an undocumented "decimal sixes" instruction that ran only in the "tags-active" mode used on AS/400, and that "generates a doubleword having 6 in each nibble where there was no carry, and 0 in each nibble that generated a carry", see https://groups.google.com/g/comp.arch/c/TgbBBxCdK0E/m/HlmFfkymuPcJ), so a case could be made. Guy Harris (talk) 19:18, 12 August 2025 (UTC)

three. I run the Libre-SOC project. https://libre-soc.org/openpower/isa/bcd/ it's a good example of "if you need it (and banking needs it, you get less errors) and don't have it, performance (and security) suck". Lkcl (talk) 21:16, 12 August 2025 (UTC)

I run the Libre-SOC project. https://libre-soc.org/openpower/isa/bcd/ Yeah, those look like the Power ISA 3.1 instructions.

it's a good example of "if you need it (and banking needs it, you get less errors) Binary can work in many cases if you treat all amounts as being in units of the smallest possible item, e.g. in the smallest currency issue with which you're dealing, so you're dealing with integers. I guess that's why DEC provided conversion instructions to 72-bit binary numbers rather than full decimal arithmetic - I think those and the string instructions were added for COBOL's benefit. Guy Harris (talk) 23:45, 12 August 2025 (UTC)

There are some cute tricks for decimal arithmetic, e.g., XS-3 encoding. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 22:01, 12 August 2025 (UTC)

that's awesome. bit 4 in 2-digit addition is the carry. Lkcl (talk) 06:42, 13 August 2025 (UTC)

The only machines that I know of with a Gray to binary (GTB) instruction are the GE-600 series and their successors. I guess they got shafted (evil grin) by the requirement. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 22:01, 12 August 2025 (UTC)

) an accumulator machine with additional registers for memory indexing, cool! well if the 2nd operand is 100% memory-based it makes sense to me. and multics! cool! I love it! and semi-SIMD for dealing with multiply and divide being a PITA producing 2x the bit-width of the input operands wooow. ok sorry, back to gray code. yeah if you need it, you need it. they clearly had a use-case. it can be micro-coded, the clue (like division on embedded systems, SuperH takes 36 cycles meaning they are using shift-subtract-shift-subtract...) is in the completion time

Lkcl (talk) 06:38, 13 August 2025 (UTC)

nope not SWAR. or I didn't read enough Lkcl (talk) 07:31, 13 August 2025 (UTC)

Yeah, n x n -> 2n multiply and 2n / n -> n quotient plus n remainder divide instructions are common (although the latter isn't guaranteed - 2n / 1 obviously doesn't generate an n-bit quotient). Guy Harris (talk) 23:05, 14 August 2025 (UTC)

ok I added a "see main section on bitmanip page" link, you can see it's a close duplication. really feel this page should stay focussed on bitmanip *sets*. not sure what to do Lkcl (talk) 21:18, 12 August 2025 (UTC)

by "not sure* I mean, option 1 move the list to the bit manipulation page, option 2 move the list *on* the bitmanip page *to* this one, or... ? Lkcl (talk) 06:18, 13 August 2025 (UTC)

References

GE 6xx

@Lkcl:I'm not sure what notable for having eight powerful tagged address registers for accessing a second operand. refers to. The 6x5 processors had a 4-bit register designater in the tag field, but that is used for address modification, not as an operand. Were you referring to the indirect tally (IT) address mode? -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 09:02, 13 August 2025 (UTC)

let's move it to the talk page on accumulator machines? Talk:Accumulator_(computing)#GE600_notability Lkcl (talk) 12:00, 13 August 2025 (UTC)

Speaking of byte manipulation, some of the "Indirect then Tally" modes in the GE 6xx/Honeywell 6000 series support 6-bit and 9-bit byte access. Guy Harris (talk) 19:54, 13 August 2025 (UTC)

Thats also true for the UNIVAC 1107 and later 1100/2200 machines, with sizes of 6, 12, and and 36. However, when I use the term byte handling I normally mean 1-bit granularity for the address and length. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 11:50, 14 August 2025 (UTC)

that sounds like they had 36-bit words and just "naturally" divided them into 1/2 and 1/4 Lkcl (talk) 12:13, 15 August 2025 (UTC)

tends to suggest that "just" byte load/store even though a quirky size .. unless it could be offset (in bit-granularity?) that would be more akin to bit-level manipulation. Lkcl (talk) 12:15, 15 August 2025 (UTC)

References

any ideas / precedent for doing "note to other editors"?

User:ULPS kindly pointed out (thank you!) the "note" is non-standard, I mean I kinda guessed that hints to editors is non-standard :) anyone know an "official" technique? there must be a template somewhere, I can't imagine this is the only time anyone has done this? https://en.m.wikipedia.org/w/index.php?title=Bit_manipulation_instructions&diff=1305796303&oldid=1305755978 Lkcl (talk) 12:22, 15 August 2025 (UTC)

A note to editors must not be a visible part of the page prose, as you had it. Occasionally notes are placed in HTML comments, in the way ULPS amended your note. Even then they are non standard and usually only left there where something is frequently changed by people who have not read the talk page. If it needs discussion or flagging, place it on the talk page. Sirfurboy🏄 (talk) 12:56, 15 August 2025 (UTC)

If the page were in Drafts, notices to editors would be appropriate. Since this is a live page, we must be more subtle. The most obvious place to discuss the page is right here on the talk page. To guide editors to particular issue on the talk page, you can use one of the many available WP:TEMPLATES on the live page. RastaKins (talk) 13:06, 15 August 2025 (UTC)

We really need a template similar to {{sic}} to mark something that is correct despite looking dubious, possibly with a |reason= parameter. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 13:24, 15 August 2025 (UTC)

thx rastakins. going to investigate & experiment Lkcl (talk) 08:40, 16 August 2025 (UTC)

took a look, closest I could find was Wikipedia:Template_index/Cleanup#Expert_needed which is "asking an expert and implying everyone else should stay away", which is not the desired goal! :) I'd like to invite collaboration rather than discourage it ;) to be honest I am surprised this hasn't come up before. certain topics just don't work well if left exclusively to Wisdom of the crowd, they need a hybrid more like a collaborative variant of the grey wolf hunting strategy https://en.m.wikiversity.org/wiki/Algorithm_models/Grey_Wolf_Optimizer Lkcl (talk) 09:09, 16 August 2025 (UTC)

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{{sic}} sounds likely? [sic]