Talk:Computer architecture

Comment 1

I'm worried about this page and a few others (one that I revised already) that 216.237.32.xxx has entered in today. They are suspiciously too good and comprehensive. I'm sure they are copied from somewhere, but I couldn't find them with a search engine. -- ansible

I'm -very- flattered. However, it's just me. Ray Van De Walker,

and I have assented to GPL my writing in the Wikipedia. If you really like it, add it to the "good writing" link! (Something which I think would be unethical for me to do as author.)

Issues with the "Power efficiency" section

Computer architecture § Power efficiency says

Modern circuits have less power required per transistor as the number of transistors per chip grows. This is because each transistor that is put in a new chip requires its own power supply and requires new pathways to be built to power it. However, the number of transistors per chip is starting to increase at a slower rate. Therefore, power efficiency is starting to become as important, if not more important than fitting more and more transistors into a single chip. Recent processor designs have shown this emphasis as they put more focus on power efficiency rather than cramming as many transistors into a single chip as possible. In the world of embedded computers, power efficiency has long been an important goal next to throughput and latency.

The statement appears to imply that merely adding additional transistors to a chip reduces the power required per transistor, but neither the article nor the first reference appear to make clear how it does so.

Perhaps there's some mechanism by which this occurs, but it would need, at minimum, a reference.

If, however, what is really meant here is that, as semiconductor process improvements shrink the size of transistors, mechanisms such as Dennard scaling cause the per-transistor power consumption to drop, as well as allowing more transistors to be put on a chip of a given size - i.e., it's not that adding more transistors to a chip reduces the power consumption per transistor, it's that shrinking transistors reduces the power consumption per transistor and allows more transistors to be put on a chip - it should be stated as such, with references.

That would also require restating the "However, the number of transistors per chip is starting to increase at a slower rate. ..." part. The Dennard scaling article speaks of the breakdown of that scaling - "leakage current and threshold voltage do not scale with size" seems to indicate that the "both voltage and current scale (downward) with length" premise in the lead of that article isn't exactly true. Perhaps, in the past, it was close enough to true that the difference between hypothetical scaling and actual scaling was minimal, and the power consumption went up sufficiently slowly as not to matter, but, at smaller sizes, that difference became significant. Guy Harris (talk) 21:24, 26 June 2025 (UTC)

As I read Dennard scaling, the big problem resulting from its breakdown appears to be that you can't just keep cranking the clock rate up without the chips eventually becoming too hot and power-hungry. Guy Harris (talk) 22:14, 26 June 2025 (UTC)

References