Tile processor

Tile processors^[1] for computer hardware, are multi-core or manycore chips that contain one-dimensional, or more commonly, two-dimensional arrays of identical tiles. Each tile comprises a compute unit (or a processing engine or CPU), caches and a switch. Conceptually, a tile is similar to a traditional CPU core (a compute unit with caches), but with an integrated switch that connects it to the on-chip network.

In a typical Tile Processor configuration, the switches in each of the tiles are connected to each other using one or more mesh networks.^[2] The Tilera TILEPro64, for example, contains 64 tiles. Each of the tiles comprises a CPU, L1 and L2 caches, and switches for several mesh networks.

Other processors in a tile configuration include SEAforth24, Kilocore KC256, XMOS xCORE microcontrollers, and some massively parallel processor arrays.

References

^ "The Tile Processor™ architecture: Embedded multicore for networking and digital multimedia - IEEE Conference Publication". August 2007: 1–12. doi:10.1109/HOTCHIPS.2007.7482495. S2CID 44858928. {{cite journal}}: Cite journal requires |journal= (help)
^ Wentzlaff, David (September 15, 2007). "On-Chip Interconnection Architecture of the Tile Processor" (PDF). IEEE Micro. doi:10.1109/MM.2007.89

This computing article is a stub. You can help Wikipedia by expanding it.

[urlThe_Tile_Processor™_architecture:_Embedded_multicore_for_networking_and_digital_multimedia_-_IEEE_Conference_Publication-1] "The Tile Processor™ architecture: Embedded multicore for networking and digital multimedia - IEEE Conference Publication". August 2007: 1–12. doi:10.1109/HOTCHIPS.2007.7482495. S2CID 44858928. {{cite journal}}: Cite journal requires |journal= (help)

[2] Wentzlaff, David (September 15, 2007). "On-Chip Interconnection Architecture of the Tile Processor" (PDF). IEEE Micro. doi:10.1109/MM.2007.89

[1]

[2]